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ASAHI KASEI
[AK5383]
AK5383
Enhanced Dual Bit 96kHz 24-Bit ADC
GENERAL DESCRIPTION The AK5383 is a 24bit, 128x oversampling 2ch A/D Converter for professional digital audio systems. The modulator in the AK5383 uses the new developed Enhanced Dual Bit architecture. This new architecture achieves the wide dynamic range, while keeping much the same superior distortion characteristics as conventional Single Bit way. The AK5383 performs 110dB dynamic range, so the device is suitable for professional studio equipment such as digital mixer, digital VTR etc. FEATURES p Enhanced Dual Bit ADC p Sampling Rate: 1kHz~108kHz p Full Differential Inputs p S/(N+D): 103dB p DR: 110dB p S/N: 110dB p High Performance Linear Phase Digital Anti-Alias filter * Passband: 0~21.768kHz(@fs=48kHz) * Ripple: 0.001dB * Stopband: 110dB p Digital HPF & Offset Calibration for Offset Cancel p Power Supply: 5V5%(Analog), 3~5.25V(Digital) p Power Dissipation: 210mW p Package: 28pin SOP, VSOP p AK5393 Pin compatible
SMODE1 SMODE2 12 VREFL GNDL VCOML AINL+ AINLZCAL AINR+ AINRVCOMR VREFR GNDR 1 2 3 4 5 6 25 24 26 28 27 23 VA 11 SCLK 14 LRCK 13 FSYNC 16 15 SDATA
Voltage Reference
Serial Output Interface
Delta-Sigma Modulator Delta-Sigma Modulator Voltage Reference
22 AGND 21 BGND
Decimation Filter Decimation Filter
HPF
19 HPFE 17 MCLK DFS
HPF
18
Controller
9 CAL 10 RST
Calibration SRAM
7 VD 8 DGND
M0049-E-03 -1-
2000/4
ASAHI KASEI
[AK5383]
n Ordering Guide
AK5383VS AK5383VF AKD5383 -10 ~ +70C 28pin SOP -40 ~ +85C 28pin VSOP AK5383 Evaluation Board
n Pin Layout
VREFL GNDL VCOML AINL+ AINLZCAL VD DGND CAL RST SMODE2 SMODE1 LRCK SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24
VREFR GNDR VCOMR AINR+ AINR-
Top View
23 22 21 20 19 18 17 16 15
VA
AGND BGND TEST HPFE DFS MCLK FSYNC SDATA
n Compatibility with AK5393
AK5393 S/(N+D) DR, S/N 105dB 117dB AK5383 103dB 110dB
M0049-E-03 -2-
2000/4
ASAHI KASEI
[AK5383]
PIN/FUNCTION
No. 1 Pin Name VREFL I/O O Function Lch Reference Voltage Pin, 3.75V Normally connected to GNDL with a 10F electrolytic capacitor and a 0.1F ceramic capacitor. Lch Reference Ground Pin, 0V Lch Common Voltage Pin, 2.75V Lch Analog positive input Pin Lch Analog negative input Pin Zero Calibration Control Pin This pin controls the calibration reference signal. "L": VCOML and VCOMR "H": Analog Input Pins (AINL, AINR) Digital Power Supply Pin, 3.3V Digital Ground Pin, 0V Calibration Active Signal Pin "H" means the offset calibration cycle is in progress. Offset calibration starts when RST goes "H". CAL goes "L" after 8704 LRCK cycles for DFS="L", 17408 LRCK cycles for DFS ="H". Reset Pin When "L", Digital section is powered-down. Upon returning "H", an offset calibration cycle is started. An offset calibration cycle should always be initiated after power-up. Serial Interface Mode Select Pin MSB first, 2's compliment. SMODE2 SMODE1 MODE LRCK L L Slave mode : MSB justified : H/L L H Master mode : Similar to I2S : H/L H L Slave mode : I2S : L/H H H Master mode : I2S : L/H Left/Right Channel Select Clock Pin LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H" during reset when SMODE1 "H".
2 3 4 5 6
GNDL VCOML AINL+ AINLZCAL
O I I I
7 8 9
VD DGND CAL
O
10
RST
I
11 12
SMODE2 SMODE1
I I
13
LRCK
I/O
M0049-E-03 -3-
2000/4
ASAHI KASEI
[AK5383]
14
SCLK
I/O
15 16
SDATA FSYNC
O I/O
17 18
MCLK DFS
I I
19
HPFE
I
20 21 22 23 24 25 26 27 28
TEST BGND AGND VA AINRAINR+ VCOMR GNDR VREFR
I I I O O
Serial Data Clock Pin Data is clocked out on the falling edge of SCLK. Slave mode: SCLK requires more than 48fs clock. Master mode: SCLK outputs a 128fs(DFS="L") or 64fs(DFS="H") clock. SCLK stays "L" during reset. Serial Data Output Pin MSB first, 2's complement. SDATA stays "L" during reset. Frame Synchronization Signal Pin Slave mode: When "H", the data bits are clocked out on SDATA. In I2S mode, FSYNC is Don't care. Master mode: FSYNC outputs 2fs clock. FSYNC stays "L" during reset. Master Clock Input Pin 256fs at DFS="L", 128fs at DFS="H". Double Speed Sampling Mode Pin "L": Normal Speed "H": Double Speed High Pass Filter Enable Pin "L": Disable "H": Enable Test Pin ( pull-down pin) Should be connected to GND. Substrate Ground Pin, 0V Analog Ground Pin, 0V Analog Supply Pin, 5V Rch Analog negative input Pin Rch Analog positive input Pin Rch Common Voltage Pin, 2.75V Rch Reference Ground Pin, 0V Rch Reference Voltage Pin, 3.75V Normally connected to GNDR with a 10F electrolytic capacitor and a 0.1F ceramic capacitor
Note: All digital inputs should not be left floating.
M0049-E-03 -4-
2000/4
ASAHI KASEI
[AK5383]
ABSOLUTE MAXIMUM RATINGS
(AGND,BGND,DGND=0V; Note 1) Parameter Analog Digital |BGND-DGND| (Note 2) Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Temperature (power applied) AK5383VS AK5383VF Storage Temperature Power Supplies: Symbol VA VD GND IIN VINA VIND Ta Ta Tstg min -0.3 -0.3 -0.3 -0.3 -10 -40 -65 max 6.0 6.0 0.3 10 VA+0.3 VD+0.3 70 85 150 Units V V V mA V V C C C
Notes: 1. All voltages with respect to ground. 2. AGND, BGND and DGND must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND,BGND,DGND=0V; Note 1) Parameter Symbol min typ 5.0 3.3 max 5.25 5.25 Units V V Power Supplies: Analog VA 4.75 (Note 3) Digital VD 3.0 Notes:1. All voltages with respect to ground. 3. The power up sequence between VA and VD is not critical.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
M0049-E-03 -5-
2000/4
ASAHI KASEI
[AK5383]
ANALOG CHARACTERISTICS (Ta=25C; VA=5.0V; VD=3.3V; AGND,BGND,DGND=0V; fs=48kHz; Signal Frequency=1kHz; 24bit Output; Measurement frequency=10Hz~20kHz; unless otherwise specified) Parameter min typ max Units
Resolution Analog Input Characteristics: S/(N+D) fs=48kHz -1dBFS -20dBFS -60dBFS fs=96kHz -1dBFS BW=40kHz -20dBFS -60dBFS Dynamic Range (-60dBFS with A-Weighted ) S/N ( A-Weighted ) Interchannel Isolation Interchannel Gain Mismatch Gain Drift Offset Error after calibration, HPF=OFF after calibration, HPF=ON Offset Drift (HPF=OFF) Offset Calibration Range (HPF=OFF) Input Voltage (AIN+)-(AIN-) Input Impedance Power Supplies Power Supply Current VA VD (fs=48kHz; DFS=L) (fs=96kHz; DFS=H) Power Dissipation Power Supply Rejection (Note 4) Note: 4. PSRR is applied to VA, VD with 1kHz, 20mVpp. 96 93 105 105 110 103 87 47 100 81 41 110 110 120 0.1 200 1 10 50 2.45 14 24 Bits dB dB dB dB dB dB dB dB dB dB ppm/C LSB24 LSB24 LSB24/C mV V k
0.5 150 1000 2.6
2.3 8
38 6 9 210 70
54 9 14 300
mA mA mA mW dB
M0049-E-03 -6-
2000/4
ASAHI KASEI
[AK5383]
FILTER CHARACTERISTICS(fs=48kHz) (Ta=25C; VA=5.0V5%; VD=3.0~5.25V; fs=48kHz, DFS=L) Parameter Symbol min typ ADC Digital Filter(Decimation LPF): Passband (Note 5) PB 0 Stopband (Note 5) SB 26.232 Passband Ripple PR Stopband Attenuation (Note 6) SA 110 Group Delay Distortion GD 0 Group Delay (Note 7) GD 38.7 ADC Digital Filter(HPF): Frequency response (Note 5) -3dB FR 1.0 -0.1dB 6.5
max 21.768 0.001
Units kHz kHz dB dB us 1/fs Hz Hz
FILTER CHARACTERISTICS(fs=96kHz) (Ta=25C; VA=5.0V5%; VD=3.0~5.25V; fs=96kHz, DFS=H) Parameter Symbol min typ ADC Digital Filter(Decimation LPF): Passband (Note 5) PB 0 Stopband (Note 5) SB 52.464 Passband Ripple PR Stopband Attenuation (Note 8) SA 110 Group Delay Distortion GD 0 Group Delay (Note 7) GD 38.8 ADC Digital Filter(HPF):
Frequency response (Note 5) -3dB -0.1dB FR 2.0 13.0
max 43.536 0.003
Units kHz kHz dB dB us 1/fs Hz Hz
Notes: 5. The passband and stopband frequencies scale with fs. 6. The analog modulator samples the input at 6.144MHz for an output word rate of 48kHz. There is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 6.144MHz 21.768kHz, where n=1,2,3***). 7. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 24bit data of both channels to the output register. 40.7/fs(DFS = "L"),40.8/fs(DFS = "H")typ. at HPF:ON. 8. The analog modulator samples the input at 6.144MHz for an output word rate of 96kHz. There is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 6.144MHz 43.536kHz, where n=1,2,3***).
M0049-E-03 -7-
2000/4
ASAHI KASEI
[AK5383]
DIGITAL CHARACTERISTICS (Ta=25C; VA=5.0V5%; VD=3.0 ~ 5.25V) Parameter Symbol min High-Level Input Voltage VIH 70%VD Low-Level Input Voltage VIL High-Level Output Voltage Iout=-20A VOH VD-0.1 Low-Level Output Voltage Iout=20A VOL Input Leakage Current Iin SWITCHING CHARACTERISTICS
(Ta=25C; VA=5.0V5%; VD=3.0 ~ 5.25V; CL=20pF) Parameter Control Clock Frequency Master Clock 256fs: Pulse width Low Pulse width High Serial Data Output Clock (SCLK) Channel Select Clock (LRCK) duty cycle Serial Interface Timing (Note 9) Slave Mode(SMODE1="L") SCLK Period SCLK Pulse width Low Pulse width High SCLK falling to LRCK Edge (Note 10) LRCK Edge to SDATA MSB Valid SCLK falling to SDATA Valid SCLK falling to FSYNC Edge Master Mode(SMODE1="H") SCLK Frequency (DFS="L") SCLK Frequency (DFS="H") duty cycle FSYNC Frequency duty cycle SCLK falling to LRCK Edge LRCK Edge to FSYNC rising SCLK falling to SDATA Valid SCLK falling to FSYNC Edge Reset/Calibration timing RST Pulse width RST falling to CAL rising RST rising to CAL falling (Note 11) RST rising to SDATA Valid (Note 11) Symbol fCLK tCLKL tCLKH fSLK fs min 0.256 29 29 1 25
typ -
max 30%VD 0.1 10
Units V V V V A
typ 12.288
max 13.824
Units MHz ns ns MHz kHz %
6.144 48
6.912 108 75
tSLK tSLKL tSLKH tSLR tDLR tDSS tSF fSLK fSLK fFSYNC tSLR tLRF tDSS tSF tRTW tRCR tRCF tRTV
144.7 65 65 -45
-45 128fs 64fs 50 2fs 50 -20 1 -20 150
45 45 45 45
ns ns ns ns ns ns ns Hz Hz % Hz % ns tslk ns ns ns ns 1/fs 1/fs
20 45 20
50 8704 8960
Notes: 9. Refer to Serial Data interface. 10. Specified LRCK edges not to coincide with the rising edges of SCLK. 11. The number of the LRCK rising edges after RST brought high at DFS="L". The value is in master mode. In slave mode it becomes one LRCK clock(1/fs) longer. When DFS="H", tRCF=17408 and tRTV=17920.
M0049-E-03 -8-
2000/4
ASAHI KASEI
[AK5383]
n Timing Diagram
LRCK
tSLK tSLKL tSLR
tSLKH
SCLK tDLR SDATA MSB MSB-1 tDSS MSB-2
Serial Data Timing (Slave Mode, FSYNC="H")
LRCK
tSLR SCLK tSF FSYNC tSF
tDLR SDATA MSB
tDSS D1 D0
Serial Data Timing (Slave Mode)
LRCK
tSLK tSLKL tSLR
tSLKH
SCLK tDSS SDATA MSB tDSS MSB-1
Serial Data Timing (I2S Slave Mode, FSYNC = Don't Care)
M0049-E-03 -9-
2000/4
ASAHI KASEI
[AK5383]
LRCK
tSLR SCLK tSF FSYNC tLRF tSF
tDSS SDATA MSB MSB-1
Serial Data Timing (Master Mode & I2S Master Mode, DFS ="L")
tRTW RST tRCF tRTV
CAL tRCR
SDATA
Reset & Calibration Timing
M0049-E-03 - 10 -
2000/4
ASAHI KASEI
[AK5383]
OPERATION OVERVIEW n System Clock Input
The external clocks which are required to operate the AK5383 are MCLK, LRCK(fs), SCLK. MCLK should be synchronized with LRCK but the phase is free of care. MCLK should be 256fs in normal sampling mode(DFS="L") and double sampling mode needs 128fs as MCLK. Table 2 illustrates standard audio word rates and corresponding frequencies used in the AK5383. As the AK5383 includes the phase detect circuit for LRCK, the AK5383 is reset automatically when the synchronization is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up. All external clocks must be present unless RST ="L", otherwise excessive current may result from abnormal operation of internal dynamic logic.
Speed LRCK (max) SCLK MCLK
Normal(DFS ="L") 54kHz ~128fs 256fs Table 1. System Clocks fs 32.0kHz 44.1kHz 48.0kHz 96.0kHz MCLK 8.1920MHz 11.2896MHz 12.2880MHz 12.2880MHz
Double(DFS ="H") 108kHz ~64fs 128fs
SCLK 4.0960MHz 5.6448MHz 6.1440MHz 6.1440MHz
Table 2. Examples of System Clock Frequency
n Serial Data Interface
The AK5383 supports four serial data formats which can be selected via SMODE1 and SMODE2 pins(Table 3). The data format is MSB-first, 2's complement. Figure Figure 1 Figure 2 Figure 3 Figure 4 SMODE2 L L H H SMODE1 Mode L H L H Slave Mode Master Mode I2S Slave Mode I2S Master Mode LRCK Lch = H, Rch =L Lch =H, Rch =L Lch =L, Rch =H Lch =L, Rch =H
Table 3. Serial I/F Format
M0049-E-03 - 11 -
2000/4
ASAHI KASEI
[AK5383]
LRCK(i)
0 1 2 3 20 21 22 23 24 25 15 0 1 2 3 20 21 22 23 24 25 0 1
SCLK(i) FSYNC(i) SDATA(o)
23 22 21 4 3 2 1 0 23 22 21 7 43 2 1 0 23 22
Lch Data
Rch Data
FSYNC(i) SDATA(o)
23 22 5 4 3 2 1 0 23 22 5 4 3 2 1 0 23
23:MSB,0:LSB
Figure 1. Serial Data Timing (Slave Mode)
LRCK(o)
0 1 2 3 20 21 22 23 24 25 15 33 34 0 1 2 3 20 21 22 23 24 25 33 34 0 1
SCLK(o) FSYNC(o) SDATA(o)
23 22 5 4 3 2 1 0 23 22 5 4 3 2 1 0 23
Lch Data
Rch Data
23:MSB,0:LSB
Figure 2. Serial Data Timing (Master mode, DFS="L")
LRCK(i)
0 1 2 3 19 20 21 22 23 24 0 1 2 3 19 20 21 22 23 24 0 1
SCLK(i) SDATA(o)
23 22 6 5 4 3 2 1 0 23 22 6 5 4 3 2 1 0 23
Lch Data
Rch Data
23:MSB,0:LSB
Figure 3. Serial Data Timing (I2S Slave mode, FSYNC: Don't care.)
LRCK(o)
0 1 2 3 20 21 22 23 24 25 15 33 34 0 1 2 3 20 21 22 23 24 25 33 34 0 1
SCLK(o) FSYNC(o) SDATA(o)
23 22 5 4 3 2 1 0 23 23 22 5 4 3 2 1 0 23
Lch Data
Rch Data
23:MSB,0:LSB
Figure 4. Serial Data Timing (I2S Master mode, DFS="L")
M0049-E-03 - 12 -
2000/4
ASAHI KASEI
[AK5383]
n Offset Calibration
When RST pin goes to "L", the digital section is powered-down. Upon returning "H", an offset calibration cycle is started. An offset calibration cycle should always be initiated after power-up. During the offset calibration cycle, the digital section of the part measures and stores the values of calibration input of each channel in registers. The calibration input value is subtracted from all future outputs. The calibration input may be obtained from either the analog input pins (AIN+/-) or the VCOM pins depending on the state of the ZCAL pin. With ZCAL "H", the analog input pin voltages are measured, and with ZCAL "L", the VCOM pin voltages are measured. The CAL output is "H" during calibration.
n Digital High Pass Filter
The AK5383 also has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1Hz at fs=48kHz and also scales with sampling rate(fs).
M0049-E-03 - 13 -
2000/4
ASAHI KASEI
[AK5383]
SYSTEM DESIGN Figure 5 and 6 show the system connection diagram. An evaluation board[AKD5383] is available which demonstrates the optimum layout, power supply arrangements and measurement results.
10 0.1 + 0.22 3 Lch+ Lch4 5 6 +3.3~5V Digital + 10 7 0.1 8 9 10 Mode Select fs System Controller 256fs@fs=48k 11 12 13 14 DGND CAL RST SMODE2 SMODE1 LRCK SCLK BGND TEST HPFE DFS MCLK FSYNC SDATA 21 20 19 18 17 16 15 VCOML AINL+ AINLZCAL VD VCOMR AINR+ 26 25 24 23 0.1 AGND 22 Rch+ Rch+ 10 +5V Analog
1 2
VREFL GNDL
VREFR GNDR
28 0.1 27 0.22
+
10
AK5383
AINRVA
Reset & Cal Control
System Ground
Analog Ground
Figure 5. Typical Connection Diagram Notes: - LRCK = fs, SCLK=64fs. - Power lines of VA and VD should be distributed separately from the point with low impedance of regulator etc. - AGND, BGND and DGND must be connected to the same analog ground plane. - All input pins except pull-down/pull-up pins should not be left floating.
Digital Ground
Analog Ground
1 2 3 4 VREFL GNDL VCOML AINL+ AINLZCAL VD DGND CAL RST SMODE2 SMODE1 LRCK SCLK VREFR GNDR VCOMR AINR+ 28 27 26 25 24 23 22 21 20 19 18 17 16 15
System Controller
5 6 7 8 9 10 11 12 13 14
AK5383
AINRVA AGND BGND TEST HPFE DFS MCLK FSYNC SDATA
Figure 6 Ground layout
M0049-E-03 - 14 -
2000/4
ASAHI KASEI 1. Grounding and Power Supply Decoupling
[AK5383]
The AK5383 requires careful attention to power supply and grounding arrangements. Analog ground and digital ground should be separate and connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5383 as possible, with the small value ceramic capacitor being the nearest. 2. On-chip voltage reference and VCOM The reference voltage for A/D converter is a differential voltage between the VREFL/R output voltage and the GNDL/R input voltage. The GNDL/R are connected to AGND and a 10uF electrolytic capacitor parallel with a 0.1uF ceramic capacitor between the VREFL/R and the GNDL/R eliminate the effects of high frequency noise. Especially a ceramic capacitor should be as near to the pins as possible. And all digital signals, especially clocks, should be kept away from the VREFL/R pins in order to avoid unwanted coupling into the AK5383. No load current may be taken from the VREFL/R pins. VCOM is a common voltage of the analog signal. In order to eliminate the effects of high frequency noise, a 0.22uF ceramic capacitor should be connected as near to the VCOM pin as possible. And all signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK5383. No load current may be drawn from the VCOM pin. 3. Analog Inputs Analog signal is differentially input into the modulator via the AIN+ and the AIN- pins. The input voltage is the difference between AIN+ and AIN- pins. The full-scale of each pin is nominally 2.45Vpp(typ). The AK5383 can accept input voltages from AGND to VA. The ADC output data format is 2's complement. The output code is 7FFFFFH(@24bit) for input above a positive full scale and 800000H(@24bit) for input below a negative full scale. The ideal code is 000000H (@24bit) with no input signal. The DC offset is removed by the offset calibration. The AK5383 samples the analog inputs at 128fs(6.144MHz @fs=48kHz,DFS="L"). The digital filter rejects noise above the stop band except for multiples of 128fs. A simple RC filter may be used to attenuate any noise around 128fs and most audio signals do not have significant energy at 128fs. The AK5383 accepts +5V supply voltage. Any voltage which exceeds the upper limit of VA+0.3V and lower limit of AGND-0.3V and any current beyond 10mA for the analog input pins(AIN+ /-) should be avoided. Excessive currents to the input pins may damage the device. Hence input pins must be protected from signals at or beyond these limits. Use caution specially in case of using 15V in other analog circuits.
M0049-E-03 - 15 -
2000/4
ASAHI KASEI
[AK5383]
Figure 7shows an input buffer circuit example 1. This is a full-differential input buffer circuit with an inverted-amp (gain :-10dB). The capacitor of 10nF between AIN+ /- decreases the clock feed through noise of modulator, and composes a 1st order LPF(fc=360kHz) with 22ohm resistor before the capacitor. This circuit also has a 1st order LPF(fc=370kHz) composed of op-amp. In this example, the internal offset is removed by self calibration. The evaluation board should be referred about the detail.
4.7k 4.7k Analog In 8.1Vpp VP+
+
910 47 470p 3k Bias
+
AK5383 22 2.45Vpp AIN+
VPNJM5532 47
910 470p 3k
+
10n 22 AIN-
VA+ VA=5V 10k VP=15V Bias + 10k 10 0.1
Bias
2.45Vpp
CAL
"L" at self calibration
ZCAL
Figure 7 Differential Input Buffer Example 1 Figure 8 shows an input buffer circuit example 2. (1st order HPF; fc=0.66Hz, Table 4, 1st order LPF; fc=590kHz, gain=14dB, Table 5). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC input, open JP1 and JP2 for XLR input). The input level of this circuit is +/-12.4Vpp (AK5383: +/-2.45Vpp Typ.).
12.4Vpp BNC JP1 Vin+ 22u 1k + NJM5534 VA XLR 0.1u 4.7k 4.7k Bias 4.7k 10k 180 2.45Vpp 1.5n 100 10k 2.45Vpp AK5383 AIN+
180
4.7k 10u JP2 Vin12.4Vpp
+ NJM5534
+ 22u 1k NJM5534
AK5383 AIN-
Figure 8 Differential Input Buffer Example 2
fin 1Hz 10Hz Frequency Response -1.56dB -0.02dB Table 4. Frequency Response of HPF Fin 20kHz 40kHz Frequency Response -0.005dB -0.02dB Table 5. Frequency Response of LPF M0049-E-03 - 16 6.144MHz -15.6dB
2000/4
ASAHI KASEI
[AK5383]
PACKAGE (AK5383VS)
28pin SOP (Unit: mm)
10.4 0.3
7.5 0.2
1.095TYP 18.70.3 2.2 0.1
+0.1 0.15-0.05
0.10
0.40.1
0.12 M 0-10
n Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate
M0049-E-03 - 17 -
+0.1 0.1-0.05
1.27
0.75 0.2 2000/4
ASAHI KASEI
[AK5383]
PACKAGE (AK5383VF)
28pin VSOP (Unit: mm)
*9.80.2 0.675 28 15 A 7.60.2 +0.1 0.15-0.05 0.10.1 Detail A 0.50.2 1.0 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10 2000/4 - 18 1.250.2
1 0.220.1
14 0.65
n Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate
M0049-E-03
*5.60.2
ASAHI KASEI
[AK5383]
MARKING (AK5383VS)
AKM JAPAN AK5383VS
XXXBYYYYC
XXXXBYYYYC: XXXB: YYYYC:
Date code identifier
Lot number (X : Digit number, B : Alpha character ) Assembly date (Y : Digit number C : Alpha character)
M0049-E-03 - 19 -
2000/4
ASAHI KASEI
[AK5383]
MARKING (AK5383VF)
AKM AK5383VF
XXXBYYYYC
XXXXBYYYYC: XXXB: YYYYC:
Date code identifier
Lot number (X : Digit number, B : Alpha character ) Assembly date (Y : Digit number C : Alpha character)
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
M0049-E-03 - 20 -
2000/4

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